hdl - Verify Parameters in Verilog -

i have created module accepts single parameter specifying byte width of module's data lines. looks like:

module wrapper# (     parameter data_byte_width = 1 ) (      din, dout, .. );     localparam data_bit_width = 8*data_byte_width;     input [data_bit_width-1:0] din;     output [data_bit_width-1:0] dout;     .....     generate         if( data_byte_width == 1 ) begin             // various modules , interconnects 1-byte data         else if( data_byte_width == 2) begin             // various modules , interconnects 2-byte data         else if....             // , on, 4, 8, , 16         else             // data_byte_width not valid value            // here want throw error         end     endgenerate      // other code  endmodule 

the problem valid widths 1, 2, 4, 8 or 16 bytes. if other value used data_byte_width, interconnects not generated @ all. xilinx doesn't seem care that. happily "generate" nothing if invalid value supplied: resulting design synthesizes not work.

is there way check value of parameter , throw error if invalid? i've tried $error , assert (as discussed here), $display (as mentioned here). xilinx refuses use of these functions, instead throwing syntax errors , refusing continiue.

ideally, i'd throw in final else within generate, i'll settle pretty @ point.

verilog not have clean solution validate parameters. @ least 1 never mentioned in version of ieee std 1364. best verilog work around use nonexistent module.

generate   // ...   else begin // invalid parameter configuration     nonexistent_module_to_throw_a_custom_error_message_for invalid_parameters();   end endgenerate 

a false alternative replace nonexistent module line with:

initial begin   $display("runtime error invalid parameter value %b",data_byte_width);   $finish(1); end 

this false alternative because synthesis tools ignore $display (i believe ignore $finish well). not know there parameter issue until simulation, after compile. nonexistent module superior because syntax clean parameter conditional compiling error. lacks message showing value of offending parameter.

a clean solution exist in systemverilog of ieee std 1800-2009 adding elaboration system tasks. looks xilinx ise not support systemverilog. xilinx vivado i'm not sure if complaint the lrm. try out if can. read full description in ieee std 1800-2012 § 20.11 elaboration system tasks. _{(*-2012 free download effort promote sv adoption. *-2009 older , still behind pay-wall. section on elaboration system tasks verbatim between 2 versions.)}

generate   // ...   else begin // invalid parameter configuration     $error("elaboration error invalid parameter value %b in", data_byte_width);      /* alternative $fatal. prevents further elaboration         happening. $error allows rest of design elaborate.        both block simulation. */     //$fatal(1,"fatal elab. error invalid parameter value %b in", data_byte_width);   end endgenerate